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ML145502 ML145503 ML145505
PCM Codec-Filter Mono-Circuit
Legacy Device: Motorola MC145502, MC145503, MC145505
The ML145502, ML145503, and ML145505 are all per channel PCM Codec-Filter mono-circuits. These devices perform the voice digitization and reconstruction as well as the band limiting and smoothing required for PCM systems. The ML145503 is a general purpose device that is offered in a 16-pin package. These are designed to operate in both synchronous and asynchronous applications and contain an on-chip precision reference voltage. The ML145505 is a synchronous device offered in a 16-pin DIP and wide body SOIC package intended for instrument use. The ML145502 is the full-featured device which presents all of the options of the chip. This device is packaged in a 22-pin DIP and a 28-pin chip carrier package These devices are pin-for-pin replacements for Motorola's first generation of MC14400/01/02/03/05 PCM mono-circuits and are upwardly compatible with the MC14404/06/07 codecs and other industry standard codecs. They also maintain compatibility with Motorola's family of MC33120 and MC3419 SLIC products. The ML1455xx family of PCM Codec-Filter mono-circuits utilizes CMOS due to its reliable low-power performance and proven capability for complex analog/digital VLSI functions. ML145502 * 22 Pin and 28 Pin Packages * Transmit Bandpass and Receive Low-Pass Filter On-Chip * Pin Selectable Mu-Law/A-Law Companding with Corresponding Data Format * On-Chip Precision Reference Voltage (3.15 V) * Power Dissipation of 50 mW, Power-Down of 0.1 mW at 5 V * Automatic Prescaler Accepts 128 kHz, 1.536, 1.544, 2.048, and 2.56 MHz for Internal Sequencing * Selectable Peak Overload Voltages (2.5, 3.15, 3.78 V) * Access to the Inverting Input of the TxI Input Operational Amplifier * Variable Data Clock Rates (64 kHz to 4.1 MHz) * Complete Access to the Three Terminal Transmit Input Operational Amplifiers * An External Precision Reference May Be Used ML145503-- Similar to the ML145502 Plus: * 16-Pin Dip and SOIC 16 Packages * Complete Access to the Three Terminal Transmit Input Operational Amplifiers ML145505 -- Somewhat Similar To ML145503 Except: * Common 64 kHz to 4.1 MHz Transmit/Receive Data Clock
16 1
P DIP 16 = EP PLASTIC DIP CASE 648
22 1
P DIP 22 = WP PLASTIC DIP CASE 708
16 1
SOG 16 = -5P SOG PACKAGE CASE 751G
PLCC 28 = -4P PLCC PACKAGE CASE 776
28 1
CROSS REFERENCE/ORDERING INFORMATION LANSDALE PACKAGE MOTOROLA P DIP 22 PLCC 28 P DIP 16 SO 16W P DIP 16 SO 16W MC145502P MC145502FN MC145503P MC145503DW MC145505P MC145505DW ML145502WP ML145502-4P ML145503EP ML145503-5P ML145505EP ML145505-5P
Note: Lansdale lead free (Pb) product, as it becomes available, will be identified by a part number prefix change from ML to MLE.
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ML145502, ML145503, ML145505
LANSDALE Semiconductor, Inc.
ML145502/03/05 PCM CODEC-FILTER MONO-CIRCUIT BLOCK DIAGRAM
RDD RxO Rx RxG Rx RxO VDD VSS VAG + + - 2.5 V REF SEQUENCE AND CONTROL RSI CIRCUITRY TRANSMIT SHIFT REGISTER TDD TDE TDC - VDD 400 A SHARED DAC 1 FREQUENCY D/A RECEIVE SHIFT REGISTER RCE RDC
/ 1, 12, 16, 20 CCI PRESCALER
CCI
MSI VLS PDI
Vref RSI TxI - Tx + Tx NOTES: -
VSS
A/D + FREQUENCY FREQUENCY
Controlled by VLS Rx 100 k (internal resistors)
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ML145502, ML145503, ML145505
LANSDALE Semiconductor, Inc.
PIN ASSIGNMENTS (DRAWINGS DO NOT REFLECT RELATIVE SIZE) ML145503EP
VAG RxO + Tx TxI - Tx Mu/A PDI VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD RDD RCE RDC TDC TDD TDE VLS VAG RxO + Tx TxI - Tx Mu/A PDI VSS
ML145505EP
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD RDD RCE DCLK CCI TDD TDE VLS
ML145502WP
Vref VAG RxO RxG RxO + Tx TxI - Tx Mu/A PDI VSS 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 RSI VDD RDD RCE RDC TDC CCI TDD TDE MSI VLS VAG RxO + Tx TxI - Tx Mu/A PDI VSS
ML145503-5P
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD RDD RCE RDC TDC TDD TDE VLS VAG RxO + Tx TxI - Tx Mu/A PDI VSS
ML145505-5P
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD RDD RCE DCLK CCI TDD TDE VLS RxG RxO + Tx NC NC TxI - Tx
ML145502-4P
RxO VAG Vref NC RSI VDD RDD 4 3 2 1 28 27 26 5 25 24 6 7 23 22 8 28-PIN PQLCC (TOP VIEW) 9 21 20 10 11 19 12 13 14 15 16 17 18 Mu/A PDI VSS NC V LS MSI TDE NC = NO CONNECTION RCE RDC TDC NC NC CCI TDD
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ML145502, ML145503, ML145505
LANSDALE Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS (Voltage Referenced to VSS)
Rating DC Supply Voltage Voltage, Any Pin to VSS DC Drain Per Pin (Excluding VDD, VSS) Operating Temperature Range Storage Temperature Range Symbol VDD, VSS V I TA Tstg Value - 0.5 to 13 - 0.5 to VDD + 0.5 10 - 40 to + 85 - 85 to + 150 Unit V V mA C C This device contains circuitry to protect against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., VSS, VDD, VLS, or VAG). Min 4.75 8.5 7.0 9.5 4.75 -- -- -- 7.5 -- -- -- -- -- 64 -- -- -- -- -- -- -- Typ 5.0 -- -- -- -- 40 50 0.1 8.0 128 1536 1544 2048 2560 -- 3.15 3.78 3.15 2.5 1.51 x Vref 1.26 x Vref Vref Max 6.3 12.6 12.6 12.6 12.6 mW 70 90 1.0 8.5 -- -- -- -- -- 4096 -- -- -- -- -- -- -- mW kHz kHz Unit V
RECOMMENDED OPERATING CONDITIONS (TA = - 40 to + 85C)
Characteristic DC Supply Voltage Dual Supplies: VDD = - VSS, (VAG = VLS = 0 V) Single Supply: VDD to VSS (VAG is an Output, VLS = VDD or VSS) ML145502, ML145503, ML145505 (Using Internal 3.15 V Reference) ML145502 Using Internal 2.5 V Reference ML145502 Using Internal 3.78 V Reference ML145502 Using External 1.5 V Reference, Referenced to V AG Power Dissipation CMOS Logic Mode (VDD to VSS = 10 V, VLS = VDD) TTL Logic Mode (VDD = + 5 V, VSS = - 5 V, VLS = VAG = 0 V) Power Down Dissipation Frame Rate Transmit and Receive Data Rate ML145503 Must Use One of These Frequencies, Relative to MSI Frequency of 8 kHz
Data Rate for ML145502, ML145505 Full Scale Analog Input and Output Level ML145503, ML145505 ML145502 (Vref = VSS )
kHz Vp
ML145502 Using an External Reference V oltage Applied at Vref Pin
RSI = VDD RSI = VSS RSI = VAG RSI = VDD RSI = VSS RSI = VAG
DIGITAL LEVELS (VSS to VDD = 4.75 V to 12.6 V, TA = - 40 to + 85C)
Characteristic Input Voltage Levels (TDE, TDC, RCE, RDC, RDD, DC, MSI, CCI, PDI) CMOS Mode (VLS = VDD, VSS is Digital Ground) TTL Mode (VLS VDD - 4.0 V, VLS is Digital Ground) "0" "1" "0" "1" Symbol VIL VIH VIL VIH Min -- 0.7 x VDD -- VLS + 2.0 V Max 0.3 x VDD -- VLS + 0.8 V -- mA IOL IOH IOL IOH 1.0 3.0 - 1.0 - 3.0 1.6 - 0.2 -- -- -- -- -- -- Unit V
Output Current for TDD (Transmit Digital Data) CMOS Mode (VLS = VDD, VSS = 0 V and is Digital Ground) (VDD = 5 V, Vout = 0.4 V) (VDD = 10 V, Vout = 0.5 V) (VDD = 5 V, Vout = 4.5 V) (VDD = 10 V, Vout = 9.5 V) TTL Mode (VLS VDD - 4.75 V, VLS = 0 V and is Digital Ground) (VOL = 0.4 V) (VOH = 2.4 V)
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ML145502, ML145503, ML145505
LANSDALE Semiconductor, Inc.
ANALOG TRANSMISSION PERFORMANCE
(VDD = + 5 V 5%, VSS = - 5 V 5%, VLS = VAG = 0 V, Vref = RSI = VSS (Internal 3.15 V Reference), 0 dBm0 = 1.546 Vrms = + 6 dBm @ 600 , TA = - 40 to + 85C, TDC = RDC = CC = 2.048 MHz, TDE = RCE = MSI = 8 kHz, Unless Otherwise Noted) End-to-End Characteristic Absolute Gain (0 dBm0 @ 1.02 kHz, TA = 25C, VDD = 5 V, VSS = - 5 V) Absolute Gain Variation with Temperature 0 to + 70C Absolute Gain Variation with Temperature - 40 to +85C Absolute Gain Variation with Power Supply (VDD = 5 V, VSS = - 5 V, 5%) Gain vs Level Tone (Relative to - 10 dBm0, 1.02 kHz) + 3 to - 40 dBm0 - 40 to - 50 dBm0 - 50 to - 55 dBm0 Min -- -- -- -- - 0.4 - 0.8 - 1.6 -- -- -- 35 29 24 27.5 35 33.1 28.2 13.2 -- -- -- - 0.3 - 1.6 -- -- -- 300 to 3000 Hz Out-of-Band Spurious at RxO (300 - 3400 Hz @ 0 dBm0 In) 4600 to 7600 Hz 7600 to 8400 Hz 8400 to 100,000 Hz Idle Channel Noise Selective @ 8 kHz, Input = VAG, 30 Hz Bandwidth Absolute Delay @ 1600 Hz (TDC = 2.048 MHz, TDE = 8 kHz) Group Delay Referenced to 1600 Hz (TDC = 2048 kHz, TDE = 8 kHz) 500 to 600 Hz 600 to 800 Hz 800 to 1000 Hz 1000 to 1600 Hz 1600 to 2600 Hz 2600 to 2800 Hz 2800 to 3000 Hz dB -- -- -- -- -- -- -- -- -- -- -- -- -- -- - 30 - 40 - 30 - 70 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 310 200 140 70 40 75 110 170 - 75 - 41 -- -- -- -- -- - 40 - 40 - 30 - 20 -- -- -- -- -- - 30 - 40 - 30 - 70 180 -- -- -- -- 90 120 160 - 80 - 41 dB dB dBm0 s s Max -- -- -- -- + 0.4 + 0.8 + 1.6 -- -- -- -- -- -- -- -- -- -- -- 15 - 69 - 23 + 0.3 0 - 28 - 60 -- Min - 0.30 -- -- -- - 0.2 - 0.4 - 0.8 - 0.25 - 0.30 - 0.45 36 29 24 28 35.5 33.5 28.5 13.5 -- -- -- - 0.15 - 0.8 -- -- -- A/D Max + 0.30 0.03 0.1 0.02 + 0.2 + 0.4 + 0.8 + 0.25 + 0.30 + 0.45 -- -- -- -- -- -- -- -- 15 - 69 - 23 + 0.15 0 - 14 - 32 - 43 Min - 0.30 -- -- -- - 0.2 - 0.4 - 0.8 - 0.25 - 0.30 - 0.45 36 30 25 28.5 36 34.2 30.0 15.0 -- -- -- - 0.15 - 0.8 -- -- -- D/A Max + 0.30 0.03 0.1 0.02 + 0.2 + 0.4 + 0.8 + 0.25 + 0.30 + 0.45 -- -- -- -- -- -- -- -- 9 - 78 0.15 + 0.15 0 - 14 - 30 - 43 dBC Unit dB dB dB dB dB
Gain vs Level Pseudo Noise (A-Law Relative to - 10 dBm0) CCITT G.714 - 10 to - 40 dBm0 - 40 to - 50 dBm0 - 50 to - 55 dBm0 Total Distortion - 1.02 kHz Tone (C-Message) 0 to - 30 dBm0 - 40 dBm0 - 45 dBm0 - 3 dBm0 - 6 to - 27 dBm0 - 34 dBm0 - 40 dBm0 - 55 dBm0
dB
Total Distortion With Pseudo Noise (A-Law) CCITT G.714
dB
Idle Channel Noise (For End-End and A/D, See Note 1) Mu-Law, C-Message Weighted A-Law, Psophometric Weighted Frequency Response (Relative to 1.02 kHz @ 0 dBm0) 15 to 60 Hz 300 to 3000 Hz 3400 Hz 4000 Hz 4600 Hz
dBrnC0 dBm0p dB
Inband Spurious (1.02 kHz @ 0 dBm0, Transmit and RxO)
dBm0
Crosstalk of 1020 Hz @ 0 dBm0 From A/D or D/A (Note 2) Intermodulation Distortion of Two Frequencies of Amplitudes - 4 to - 21 dBm0 from the Range 300 to 3400 Hz
NOTES: 1. Extrapolated from a 1020 Hz @ - 50 dBm0 distortion measurement to correct for encoder enhancement. 2. Selectively measured while the A/D is stimulated with 2667 Hz @ - 50 dBm0.
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ML145502, ML145503, ML145505
LANSDALE Semiconductor, Inc.
ANALOG ELECTRICAL CHARACTERISTICS (VDD = - VSS = 5 V to 6 V 5%, TA = - 40 to + 85C)
Characteristic Input Current AC Input Impedance to VAG (1 kHz) Input Capacitance Input Offset Voltage of Txl Op Amp Input Common Mode Voltage Range Input Common Mode Rejection Ratio Txl Unity Gain Bandwidth Txl Open Loop Gain +Tx, -Tx +Tx, -Tx RL 10 k RL 10 k VICR CMRR BWp AVOL +Tx, -Tx +Tx, -Tx +Tx, -Tx Symbol Iin Zin Min -- 5 -- -- VSS + 1.0 -- -- -- -- 0 Vout VSS + 0.8 VSS + 1.5 5.5 Zout -- 0 RxO RxO* -- -- 62 0.5 -- -- Source Sink IVAG 0.4 10.0 -- 45 55 50 50 -- -- -- 3 -- -- -- 100 -- -- 0.53 VDD + 0.47 VSS -- -- -- 50 65 55 60 VDD - 1.0 VDD - 1.5 -- -- 200 100 150 225 VDD - 1.0 20 -- 0.8 -- 30 -- -- -- -- mA pF mV k V A V mA A dBC dBC Typ 0.01 10 -- < 30 -- 70 1000 75 - 20 -- Max 0.2 -- -- 10 -- VDD - 2.0 -- -- -- -- 100 Unit A M pF mV V dB kHz dB dBrnC0 pF V
Equivalent Input Noise (C-Message) Between +Tx and -Tx, at Txl Output Load Capacitance for Txl Op Amp Output Voltage Range Txl Op Amp, RxO or RxO RL = 10 k to VAG RL = 600 to VAG Output Current Txl, RxO, RxO Output Impedance RxO, RxO* Output Load Capacitance for RxO and RxO* Output dc Offset Voltage Referenced to VAG Pin Internal Gainsetting Resistors for RxG to RxO and RxO External Reference Voltage Applied to Vref (Referenced to VAG) Vref Input Current VAG Output Bias Voltage VAG Output Current VSS + 1.5 V Vout VDD - 1.5 V 0 to 3.4 kHz
Output Leakage Current During Power Down for the Txl Op Amp, VAG, RxO, and RxO Positive Power Supply Rejection Ratio, 0 - 100 kHz @ 250 mV, C-Message Weighting Negative Power Supply Rejection Ratio, 0 - 100 kHz @ 250 mV, C-Message Weighting Transmit Receive Transmit Receive
* Assumes that RxG is not connected for gain modifications to RxO.
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LANSDALE Semiconductor, Inc.
MODE CONTROL LOGIC (VSS to VDD = 4.75 V to 12.6 V, TA = - 40 to + 85C)
Characteristic VLS Voltage for TTL Mode (TTL Logic Levels Referenced to VLS) VLS Voltage for CMOS Mode (CMOS Logic Levels of VSS to VDD) Mu/A Select Voltage Mu-Law Mode Sign Magnitude Mode A-Law Mode RSI Voltage for Reference Select Input (ML145502) 3.78 V Mode 2.5 V Mode 3.15 V Mode Min VSS VDD - 0.5 VDD - 0.5 VAG - 0.5 VSS VDD - 0.5 VAG - 0.5 VSS VSS VAG + 0.5 -- Typ -- -- -- -- -- -- -- -- -- -- 128 Max VDD - 4.0 VDD VDD VAG + 0.5 VSS + 0.5 VDD VAG + 0.5 VSS + 0.5 VSS + 0.5 VDD - 1.0 -- kHz V Unit V V V
Vref Voltage for Internal or External Reference (ML145502 Only) Internal Reference Mode External Reference Mode Analog Test Mode Frequency, MS = CCI (ML145502 Only) See Pin Description; Test Modes
V
SWITCHING CHARACTERISTICS (VSS to VDD = 9.5 V to 12.6 V, TA = - 40 to + 85C, CL = 150 pF, CMOS or TTL Mode)
Characteristic Output Rise Time Output Fall Time Input Rise Time Input Fall Time Pulse Width TDD TDE, TDC, RCE, RDC, DC, MSI, CCI TDE Low, TDC, RCE, RDC, DC, MSI, CCI TDC, RDC, DC Symbol tTLH tTHL tTLH tTHL tw fCL fCL1 fCL2 fCL3 fCL4 fCL5 tP1 tP2 tP3 tP4 tsu1 tsu2 tsu8 tsu3 tsu4 tsu5 tsu6 tsu7 th Min -- -- -- -- 100 64 -- -- -- -- -- -- -- -- -- -- -- -- -- 20 100 20 20 100 60 20 100 100 -- -- -- -- Typ 30 30 -- -- -- -- 128 1536 1544 2048 2560 90 90 -- -- 90 90 90 90 -- -- -- -- -- -- -- -- -- -- 0.01 12 0.1 Max 80 80 4 4 -- 4096 -- -- -- -- -- 180 150 55 40 180 150 180 150 -- -- -- -- -- -- -- -- -- 10 10 15 10.0 ns ns ns ns ns ns ns ns ns pF A pF A Unit ns s ns kHz kHz
DCLK Pulse Frequency (ML145502/05 Only)
CCI Clock Pulse Frequency (MSI = 8 kHz) CCI is internally tied to TDC on the ML145503, therefore, the transmit data clock must be one of these frequencies. This pin will accept one of these discrete clock frequencies and will compensate to produce internal sequencing. Propagation Delay Time TDE Rising to TDD Low Impedance TDE Falling to TDD High Impedance TDC Rising Edge to TDD Data, During TDE High TDE Rising Edge to TDD Data, During TDC High TDC Falling Edge to TDE Rising Edge Setup Time TDE Rising Edge to TDC Falling Edge Setup Time TDE Falling Edge to TDC Rising Edge to Preserve the Next TDD Data RDC Falling Edge to RCE Rising Edge Setup Time RCE Rising Edge to RDC Falling Edge Setup Time RDD Valid to RDC Falling Edge Setup Time CCI Falling Edge to MSI Rising Edge Setup Time MSI Rising Edge to CCI Falling Edge Setup Time RDD Hold Time from RDC Falling Edge TDE, TDC, RCE, RDC, RDD, DC, MSI, CCI Input Capacitance TDE,TDC, RCE, RDC, RDD, DC, MSI, CCI Input Current TDD Capacitance During High Impedance (TDE Low) TDD Input Current During High Impedance (TDE Low) TTL CMOS TTL CMOS TTL CMOS TTL CMOS
ns
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ML145502, ML145503, ML145505
LANSDALE Semiconductor, Inc.
DEVICE DESCRIPTIONS A codec-filter is a device which is used for digitizing and reconstructing the human voice. These devices were developed primarily for the telephone network to facilitate voice switching and transmission. Once the voice is digitized, it may be switched by digital switching methods or transmitted long distance (T1, microwave, satellites, etc.) without degradation. The name codec is an acronym from "Coder" for the A/D used to digitize voice, and "Decoder" for the D/A used for reconstructing voice. A codec is a single device that does both the A/D and D/A conversions. To digitize intelligible voice requires a signal to distortion of about 30 dB for a dynamic range of about 40 dB. This may be accomplished with a linear 13-bit A/D and D/A, but will far exceed the required signal to distortion at amplitudes greater than 40 dB below the peak amplitude. This excess performance is at the expense of data per sample. Two methods of data reduction are implemented by compressing the 13-bit linear scheme to companded 8-bit schemes. These companding schemes follow a segmented or "piecewise-linear"curve formatted as sign bit, three chord bits, and four stepbits. For a given chord, all 16 of the steps have the same voltage weighting. As the voltage of the analog input increases, the four step bits increment and carry to the three chord bits which increment. With the chord bits incremented, the step bits double their voltage weighting. This results in an effective resolution of 6-bits (sign + chord + four step bits) across a 42 dB dynamic range (7 chords above zero, by 6 dB per chord). There are two companding schemes used; Mu-255 Law specifically in North America, and A-Law specifically in Europe. These companding schemes are accepted worldwide. The tables show the linear quantization levels to PCM words for the two companding schemes. In a sampling environment, Nyquist theory says that to properly sample a continuous signal, it must be sampled at a frequency higher than twice the signal's highest frequency component. Voice contains spectral energy above 3 kHz, but its absence is not detrimental to intelligibility. To reduce the digital data rate, which is proportional to the sampling rate, a sample rate of 8 kHz was adopted, consistent with a band-width of 3 kHz. This sampling requires a low-pass filter to limit the high frequency energy above 3 kHz from distorting the inband signal. The telephone line is also subject to 50/60 Hz power line coupling which must be attenuated from the signal by a high-pass filter before the A/D converter. The D/A process recon-
structs a staircase version of the desired inband signal which has spectral images of the in-band signal modulated about the sample frequency and its harmonics. These spectral images are called aliasing components which need to be attenuated to obtain the desired signal. The low-pass filter used to attenuate filter aliasing components is typically called a reconstruction or smoothing filter. The ML1455XX series PCM Codec-Filters have the codec, both presampling and reconstruction filters, a precision voltage reference on chip, and require no external components. There are three distinct versions of the Lansdale ML1455XX Series. ML145502 The ML145502 PCM Codec-Filter is the full feature 22-pin device. It is intended for use in applications requiring maximum flexibility. The ML145502 is intended for bit interleaved or byte interleaved applications with data clock frequencies which are nonstandard or time varying. One of the five standard frequencies (see ML145503 below) is applied to the CCI input, and the data clock inputs can be any frequency between 64 kHz and 4.096 MHz. The Vref pin allows for use of an external shared reference or selection of the internal reference. The RxG pin accommodates gain adjustments for the inverted analog output. All three pins of the input gain-setting operational amplifier are present, providing maximum flexibility for the analog interface. ML145503 The ML145503 PCM Codec-Filter is intended for standard byte interleaved synchronous or asynchronous applications. TDC can be one of five discrete frequencies. These are 128 kHz (40 to 60% duty cycle), 1.536, 1.544, 2.048, or 2.56 MHz. (For other data clock frequencies, see ML145502 or ML145505.) The internal reference is set for 3.15 V peak full scale, and the full scale input level at Txl and output level at RxO is 6.3 V peak-to-peak. This is the + 3 dBm0 level of the PCM Codec-Filter. The +Tx and -Tx inputs provide maximum flexibility for analog interface. All other functions are described in the pin description. ML145505 The ML145505 PCM Codec-Filter is intended for byte interleaved synchronous applications. The ML145505 has all the features of the ML145503 but internally connects TDC and RDC (see pin description) to the DC pin. One of the five standard frequencies (listed above) should be applied to CCI. The data clock input (DC) can be any frequency between 64 kHz and 4.096 MHz.
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ML145502, ML145503, ML145505
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PIN DESCRIPTIONS DIGITAL VLS Logic Level Select input and TTL Digital Ground VLS controls the logic levels and digital ground reference for all digital inputs and the digital output. These devices can operate with logic levels from full supply (VSS to VDD) or with TTL logic levels using VLS as digital ground. For VLS = VDD, all I/O is full supply (VSS to VDD swing) with CMOS switch points. For VSS < VLS < (VDD - 4 V), all inputs and outputs are TTL compatible with VLS being the digital ground. The pins controlled by V are inputs MSI, CCI, TDE, TDC, RCE, RDC, RDD, PDI, and output TDD. MSI Master Synchronization Input MSI is used for determining the sample rate of the transmit side and as a time base for selecting the internal prescale divider for the convert clock input (CCI) pin. The MSI pin should be tied to an 8 kHz clock which may be a frame sync or system sync signal. MSI has no relation to transmit or receive data timing, except for determining the internal transmit strobe as described under the TDE pin description. MSI should be derived from the transmit timing in asynchronous applications. In many applications MSI can be tied to TDE. (MSI is tied internally to TDE in ML145503/05.) CCI Convert Clock Input CCI is designed to accept five discrete clock frequencies. These are 128 kHz, 1.536 MHz, 1.544 MHz, 2.048 MHz, or 2.56 MHz. The frequency at this input is compared with MSI and prescale divided to produce the internal sequencing clock at 128 kHz (or 16 times the sampling rate). The duty cycle of CCI is dictated by the minimum pulse width except for 128 kHz, which is used directly for internal sequencing and must have a 40 to 60% duty cycle. In asynchronous applications, CCI should be derived from transmit timing. (CCI is tied internally to TDC in ML145503.) TDC Transmit Data Clock Input TDC can be any frequency from 64 kHz to 4.096 MHz, and is often tied to CCI if the data rate is equal to one of the five discrete frequencies. This clock is the shift clock for the transmit shift register and its rising edges produce successive data bits at TDD. TDE should be derived from this clock. (TDC and RDC are tied together internally in the ML145505 and are called DC.) CCI is internally tied to TDC on the ML145503. Therefore, TDC must satisfy CCI timing requirements also. TDE Transmit Data Enable Input TDE serves three major functions. The first TDE rising edge following an MSI rising edge generates the internal transmit strobe which initiates an A/D conversion. The internal transmit strobe also transfers a new PCM data word into the transmit shift register (sign bit first) ready to be output at TDD. The TDE pin is the high impedance control for the transmit digital data (TDD) output. As long as this pin is high, the TDD output stays low impedance. This pin also enables
the output shift register for clocking out the 8-bit serial PCM word. The logical AND of the TDE pin with the TDC pinclocks out a new data bit at TDD. TDE should be held high for eight consecutive TDC cycles to clock out a complete PCM word for byte interleaved applications. The transmit shift register feeds back on itself to allow multiple reads of the transmit data. If the PCM word is clocked out once per frame in a byte interleaved system, the MSI pin function is transparent and may be connected to TDE. The TDE pin may be cycled during a PCM word for bit interleaved applications. TDE controls both the high impedance state of the TDD output and the internal shift clock. TDE must fall before TDC rises (tsu8) to ensure integrity of the next data bit. There must be at least two TDC falling edges between the last TDE rising edge of one frame and the first TDE rising edge of the next frame. MSI must be available separate from TDE for bit interleaved applications. TDD Transmit Digital Data Output The output levels at this pin are controlled by the VLS pin. For VLS connected to VDD, the output levels are from VSS to VDD. For a voltage of VLS between VDD - 4 V and VSS, the output levels are TTL compatible with VLS being the digital ground supply. The TDD pin is a three-state output controlled by the TDE pin. The timing of this pin is controlled by TDC and TDE. When in TTL mode, this output may be made high-speed CMOS compatible using a pull-up resistor. The data format (Mu-Law, A-Law, or sign magnitude) is controlled by the Mu/A pin. RDC Receive Data Clock Input RDC can be any frequency from 64 kHz to 4.096 MHz. This pin is often tied to the TDC pin for applications that can use a common clock for both transmit and receive data transfers. The receive shift register is controlled by the receive clock enable (RCE) pin to clock data into the receive digital data (RDD) pin on falling RDC edges. These three signals can be asynchronous with all other digital pins. The RDC input is internally tied to the TDC input on the ML145505 and called DC. RCE Receive Clock Enable Input The rising edge of RCE should identify the sign bit of a receive PCM word on RDD. The next falling edge of RDC, after a rising RCE, loads the first bit of the PCM word into the receive register. The next seven falling edges enter the remainder of the PCM word. On the ninth rising edge, the receive PCM word is transferred to the receive buffer register and the A/D sequence is interrupted to commence the decode process. In asynchronous applications with an 8 kHz transmit sample rate, the receive sample rate should be between 7.5 and 8.5 kHz. Two receive PCM words may be decoded and analog summed each transmit frame to allow on-chip conferencing. The two PCM words should be clocked in as two single PCM words, a minimum of 31.25 s apart, with a receive data clock of 512 kHz or faster.
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LANSDALE Semiconductor, Inc.
RDD Receive Digital Data Input RDD is the receive digital data input. The timing for this pin is controlled by RDC and RCE. The data format is determined by the Mu/A pin. Mu/A Select This pin selects the companding law and the data format at TDD and RDD. Mu/A = VDD; Mu-255 Companding D3 Data Format with Zero Code Suppress Mu/A = VAG; Mu-255 Companding with Sign Magnitude Data Format Mu/A = VSS; A-Law Companding with CCITT Data Format Bit Inversions
Code + Full Scale + Zero - Zero - Full Scale SIGN BIT 0 1 Sign/ Magnitude 1111 1111 1000 0000 0000 0000 0111 1111 Mu-Law 1000 1111 0111 0000 0000 1111 1111 0010 A-Law (CCITT) 1010 1101 0101 0010 1010 0101 0101 1010
CHORD BITS 2 3 4
STEP BITS 5 6 7
NOTE: Starting from sign magnitude, to change format: To Mu-Law -- MSB is unchanged (sign) Invert remaining seven bits If code is 0000 0000, change to 0000 0010 (for zero code suppression) To A-Law -- MSB is unchanged (sign) Invert odd numbered bits Ignore zero code suppression
PDI Power Down Input The power down input disables the bias circuitry and gates off all clock inputs. This puts the VAG, Txl, RxO, RxO, and TDD outputs into a high-impedance state. The power dissipation is reduced to 0.1 mW when PDI is a low logic level. The circuit operates normally with PDI = VDD or with a logic high as defined by connection at VLS. TDD will not come out of high impedance for two MSI cycles after PDI goes high. DCLK Data Clock Input In the ML145505, TDC and RDC are internally connected to DCLK. ANALOG V AG Analog Ground input/Output Pin
VAG is the analog ground power supply input/output. All analog signals into and out of the device use this as their ground reference. Each version of the ML1455xx PCM Codec-Filter family can provide its own analog ground supply internally. The DC voltage of this internal supply is 6% positive of the midway between VDD and VSS. This supply can sink more than 8 mA but has a current source limited to 400 A.The output of this supply is internally connected to the analog ground input of the part. The node where this supply and the analog ground are connected is brought out to the VAG pin. In symmetric dual supply systems (5, 6, etc.), VAG may be externally tied to the system analog ground supply. When RxO or RxO drive low impedance loads tied to VAG, a pull-up resistor to VDD will be required to boost the source current capability if VAG is not tied to the supply ground. All analog signals for the part are referenced to VAG, including noise; therefore, decoupling capacitors (0.1 F) should be used from VDD to VAG and VSS to VAG. Vref Positive Voltage Reference Input (ML145502 Only) The Vref pin allows an external reference voltage to be used for the A/D and D/A conversions. If Vref is tied to VSS, the internal reference is selected. If Vref > VAG, then the external mode is selected and the voltage applied to Vref is used for generating the internal converter reference voltage. In either internal or external reference mode, the actual voltage used for conversion is multiplied by the ratio selected by the RSI pin. The RSI pin circuitry is explained under its pin description below. Both the internal and external references are inverted within the PCM Codec-Filter for negative input voltages such that only one reference is required. External Mode -- In the external reference mode (Vref >VAG), a 2.5 V reference like the MC1403 may be connected from Vref to VAG. A single external reference may be shared by tying together a number of Vref pins and VAG pins from different codec-filters. In special applications, the external reference voltage may be between 0.5 and 5 V However, the reference voltage gain selection circuitry . associated with RSI must be considered to arrive at the desired codec-filter gain. Internal Mode -- In the internal reference mode (Vref =VSS), an internal 2.5 V reference supplies the reference voltage for the RSI circuitry. The Vref pin is functionally connected to VSS for the ML145503,and ML145505 pinouts. RSI Reference Select Input (ML145502 Only) The RSI input allows the selection of three different overload or full-scale A/D and D/A converter reference voltages independent of the internal or external reference mode. The RSI pin is a digital input that senses three different logic states: VSS, VAG, and VDD. For RSI = VAG, the reference voltage is used directly for the converters. The internal reference is 2.5 V For RSI = VSS, the reference . voltage is multiplied by the ratio of 1.26, which results in an internal converter reference of 3.15 V For RSI = VDD, the reference voltage . is multiplied by 1.51, which results in an internal converter reference of 3.78 V The device requires a minimum of 1.0 V of headroom . between the internal converter reference to VDD. VSS has this same absolute valued minimum, also measured from VAG pin. The various modes of operation are summarized in Table 2. The RSI pin is functionally connected to VSS for the ML145503, and ML145505 pinouts.
Issue A
Page 10 of 26
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ML145502, ML145503, ML145505
LANSDALE Semiconductor, Inc.
RxO, RxO Receive Analog Outputs These two complimentary outputs are generated from the output of the receive filter. They are equal in magnitude and out of phase. The maximum signal output of each is equal to the maximum peak-to-peak signal described with the reference. If a 3.15 V reference is used with RSI tied to VAG and a + 3 dBm0 sine wave is decoded, the RxO output will be a 6.3 V peak-to-peak signal. RxO will also have an inverted signal output of 6.3 V peak-to-peak. External loads may be connected from RxO to RxO for a 6 dB push-pull signal gain or from either RxO or RxO to VAG. With a 3.15 V reference each output will drive 600 to + 9 dBm. With RSI tied to VDD, each output will drive 900 to + 9 dBm. RxG Receive Output Gain Adjust (ML145502 Only) The purpose of the RxG pin is to allow external gain adjustment for the RxO pin. If RxG is left open, then the output signal at RxO will be inverted and output at RxO. Thus the push-pull gain to a load from RxO to RxO is two times the output level at RxO. If external resistors are applied from RxO to RxG (RI) and from RxG to RxO (RG), the gain of RxO can be set differently from inverting unity. These resistors should be in the range of 10 k. The RxO output level is unchanged by the resistors and the RxO gain is approximately equal to minus RG/RI. The actual gain is determined by taking into account the internal resistors which will be in parallel to these external resistors. The internal resistors have a large tolerance, but they match each other very closely. This matching tends to minimize the effects of their tolerance on external gain configurations. The circuit for RxG and RxO is shown in the block diagram. Txl Transmit Analog Input TxI is the input to the transmit filter. It is also the output of the transmit gain amplifiers of the ML145502/03/05. The TxI input has an internal gain of 1.0, such that a +3 dBm0 signal at TxI corresponds to the peak converter reference voltage as described in the Vref and RSI pin descriptions. For 3.15 V reference, the + 3 dBm0 input should be 6.3 V peak-to-peak.
+Tx/-Tx Positive Tx Amplifier Input Negative Tx Amplifier Input The Txl pin is the input to the transmit band-pass filter. If +Tx or -Tx is available, then there is an internal amplifier preceding the filter whose pins are +Tx, -Tx, and TxI. These pins allow access to the amplifier terminals to tailor the input gain with external resistors. The resistors should be in the range of 10 k. If +Tx is not available, it is internally tied to VAG. If -Tx and +Tx are not available, the TxI is a unity gain high-impedance input. POWER SUPPLIES VDD Most Positive Power Supply VDD is typically 5 to 12 V. VSS Most Negative Power Supply VSS is typically 10 to 12 V negative of VDD. For a 5 V dual-supply system, the typical power supply configuration is VDD = + 5 V, VSS = - 5 V, VLS = 0 V (digital ground accommodating TTL logic levels), and VAG = 0 V being tied to system analog ground. For single-supply applications, typical power supply configurations include: VDD = 10 V to 12 V VSS = 0 V VAG generates a mid supply voltage for referencing all analog signals. VLS controls the logic levels. This pin should be connected to VDD for CMOS logic levels from VSS to VDD. This pin should be connected to digital ground for true TTL logic levels referenced to VLS. TESTING CONSIDERATIONS (ML145502 ONLY) An analog test mode is activated by connecting MSI and CCI to 128 kHz. In this mode, the input of the A/D (the output of the Tx filter) is available at the PDI pin. This input is direct coupled to the A/D side of the codec. The A/D is a differential design. This results in the gain of this input being effectively attenuated by half. If monitored with a high-impedance buffer, the output of the Tx low-pass filter can also be measured at the PDI pin. This test mode allows independent evaluation of the transmit low-pass filter and A/D side of the codec. The transmit and receive channels of these devices are tested with the codec-filter fully functional.
Page 11 of 26
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Issue A
ML145502, ML145503, ML145505
LANSDALE Semiconductor, Inc.
VAG 600 Rx 5 k Tx 681 10 k
ML145503 1 2 3 4 5 6 7 VAG RxO + Tx TxI - Tx Mu/A PDI VDD RDD RCE RDC TDC TDD TDE 16 15 14 13 12 11 10
51 k*
5V 0.1 F
ENABLE CLOCK
8V SS 0.1 F -5V * To define RDD when TDD is high Z.
VLS 9
Figure 1. Test Circuit
Table 1. Options Available by Pin Selection
RSI* Pin Level VDD VDD VAG VAG VSS VSS Vref* Pin Level VSS VAG + VEXT VSS VAG + VEXT VSS VAG + VEXT Peak-to-Peak Overload Voltage (Txl, RxO) 7.56 V p-p (3.02 x VEXT) V p-p 5 V p-p (2 x VEXT) V p-p 6.3 V p-p (2.52 x VEXT) V p-p
* On ML145503/05, RSI and Vref tied internally to V SS .
Table 2. Summary of Operation Conditions User Programmed Through Pins VDD, VAG, and VSS
Pin Programmed Logic Level VDD VAG VSS Mu/A Mu-Law Companding Curve and D3/D4 Digital Formats with Zero Code Suppress Mu-Law Companding Curve and Sign Magnitude Data Format A-Law Companding Curve and CCITT Digital Format RSI Peak Overload Voltage 3.78 2.50 3.15
VLS CMOS Logic Levels TTL Levels VAG Up TTL Levels VSS Up
Page 12 of 26
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ML145502, ML145503, ML145505
LANSDALE Semiconductor, Inc.
TDE tsu2 TDC tP1 TDD tP4 tsu1 1 tP3 2 3 tP3 4 5 fCL tw 6 7 8 tP2 LSB PCM WORD REPEATED 9 tw tsu8 10 11 tP2
*
MSB
* Data output during this time will vary depending on TDC rate and TDE timing.
Figure 2. Transmit Timing Diagram
tw RCE tsu4 tsu3 RDC tsu5 DON'T CARE 1 2 th MSB LSB DON'T CARE 3 4 fCL tw 5 6 7 8 9 10 11 tw
RDD
Figure 3. Receive Timing Diagram
tw MSI tsu7 tsu6 CCI 1 2 3 4 5 6 7 tw tw 8 9 10 11
Figure 4. MSI/CCI Timing Diagram
Page 13 of 26
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ML145502, ML145503, ML145505
LANSDALE Semiconductor, Inc.
1.00 0.80 0.60 GAIN ERROR (dB) 0.40 0.20 0 - 0.20 - 0.40 - 0.60 - 0.80 - 1.00 - 60 - 50 TYPICAL PEFORMANCE GUARANTEED PERFORMANCE
VDD = + 5 V VSS = - 5 V 2048 kHz CLOCK GAIN ERROR (dB)
1.00 0.80 0.60 0.40 0.20 0 - 0.20 - 0.40 - 0.60 - 0.80 - 1.00 - 60 TYPICAL PEFORMANCE GUARANTEED PERFORMANCE
VDD = + 5 V VSS = - 5 V 2048 kHz CLOCK
- 40 - 30 - 20 - 10 INPUT LEVEL AT 1.02 kHz
0
- 50
- 40 - 30 - 20 INPUT LEVEL AT 1.02 kHz
- 10
0
Figure 5. ML145502 Gain vs Level Mu-Law Transmit
Figure 6. ML145502 Gain vs Level Mu-Law Receive
45.0 QUANTIZTION DISTORTION (dB) QUANTIZTION DISTORTION (dB) 40.0 35.0 30.0 25.0 20.0 15.0 10.0 - 60 TYPICAL PEFORMANCE C-MESSAGE WEIGHTED VDD = + 5 V VSS = - 5 V 2048 kHz CLOCK
45.0 40.0 35.0 30.0 25.0 20.0 15.0 10.0 - 60 TYPICAL PEFORMANCE C-MESSAGE WEIGHTED VDD = + 5 V VSS = - 5 V 2048 kHz CLOCK GUARANTEED PERFORMANCE
GUARANTEED PERFORMANCE
- 50
- 40 - 30 - 20 - 10 INPUT LEVEL AT 1.02 kHz
0
- 50
- 40 - 30 - 20 - 10 INPUT LEVEL AT 1.02 kHz
0
Figure 7. ML145502 Quantization Distortion Mu-Law Transmit
Figure 8. ML145502 Quantization Distortion Mu-Law Receive
0.8 0.6 0.4 GAIN ERROR (dB) 0.2 0 - 0.2 - 0.4 - 0.6 - 0.8 - 60 - 50 GUARANTEED PERFORMANCE - 40 - 30 - 20 - 10 VDD = + 5 V VSS = - 5 V 2048 kHz CLOCK GAIN ERROR (dB) TYPICAL PEFORMANCE
0.8 0.6 0.4 0.2 0 - 0.2 - 0.4 - 0.6 - 0.8 - 60 - 50 - 40 - 30 - 20 - 10 GUARANTEED PERFORMANCE VDD = + 5 V VSS = - 5 V 2048 kHz CLOCK TYPICAL PEFORMANCE
INPUT LEVEL PSEUDO NOISE (dBm0)
INPUT LEVEL PSEUDO NOISE (dBm0)
Figure 9. ML145502 Gain vs Level A-Law Transmit
Figure 10. ML145502 Gain vs Level A-Law Receive
Page 14 of 26
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Issue A
ML145502, ML145503, ML145505
LANSDALE Semiconductor, Inc.
QUANTIZATION DISTORTION (dB)
QUANTIZATION DISTORTION (dB)
40.0 35.0 30.0 25.0 20.0 15.0 10.0 - 60 - 50 - 40 - 30 TYPICAL PERFORMANCE GUARANTEED PERFORMANCE PSOPHOMETRIC WEIGHTED VDD = + 5 V VSS = - 5 V 2048 kHz - 20 - 10 0
40.0 35.0 30.0 25.0 20.0 15.0 10.0 - 60
TYPICAL PERFORMANCE
GUARANTEED PERFORMANCE
PSOPHOMETRIC WEIGHTED VDD = + 5 V VSS = - 5 V 2048 kHz - 50 - 40 - 30 - 20 - 10 0
INPUT LEVEL PSEUDO NOISE (dBm0)
INPUT LEVEL PSEUDO NOISE (dBm0)
Figure 11. ML145502 Quantization Distortion A-Law Transmit
Figure 12. ML145502 Quantization Distortion A-Law Receive
POWER SUPPLY REJECTION (dB)
TYPICAL PERFORMANCE
60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 80 90 100 FREQUENCY (kHz)
POWER SUPPLY REJECTION (dB)
70
70 60 50 40 30 20 10 0 0 10 20
TYPICAL PERFORMANCE
30
40
50
60
70
80
90
100
FREQUENCY (kHz)
Figure 13. ML145502 Power Supply Rejection Ratio Positive Transmit VAC = 250 mVrms, C-Message Weighted
Figure 14. ML145502 Power Supply Rejection Ratio Negative Transmit VAC = 250 mVrms, C-Message Weighted
POWER SUPPLY REJECTION (dB)
TYPICAL PERFORMANCE 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 80 90 100 FREQUENCY (kHz)
POWER SUPPLY REJECTION (dB)
70
70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 80 90 100 TYPICAL PERFORMANCE
FREQUENCY (kHz)
Figure 15. ML145502 Power Supply Rejection Ratio Positive Receive VAC = 250 mVrms, C-Message Weighted
Figure 16. ML145502 Power Supply Rejection Ratio Negative Receive VAC = 250 mVrms, C-Message Weighted
Page 15 of 26
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ML145502, ML145503, ML145505
LANSDALE Semiconductor, Inc.
0.2 0.1 0 - 0.1 GAIN (dB) - 0.2 - 0.3 - 0.4 - 0.5 - 0.6 - 0.7 - 0.8 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 FREQUENCY (kHz) TYPICAL PERFORMANCE GUARANTEED PERFORMANCE GAIN (dB)
2.0 0 - 2.0 - 4.0 - 6.0 - 8.0 - 10.0 - 12.0 - 14.0 - 16.0 - 18.0 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 FREQUENCY (kHz) GUARANTEED PERFORMANCE TYPICAL PERFORMANCE GUARANTEED PERFORMANCE
Figure 17. ML145502 Pass-Band Filter Response Transmit
Figure 18. ML145502 Low-Pass Filter Response Transmit
2.0 - 2.0 - 6.0 GAIN (dB) GAIN (dB) - 10.0 - 14.0 - 18.0 - 22.0 - 26.0 - 30.0 0 0.04 0.08 0.12 0.16 FREQUENCY (kHz) 0.20 0.24 GUARANTEED PERFORMANCE TYPICAL PERFORMANCE
0.2 0.1 0 - 0.1 - 0.2 - 0.3 - 0.4 - 0.5 - 0.6 - 0.7 - 0.8 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 FREQUENCY (kHz) TYPICAL PERFORMANCE GUARANTEED PERFORMANCE
Figure 19. ML145502 High-Pass Filter Response Transmit
Figure 20. ML145502 Pass-Band Filter Response Receive
2.0 0 - 2.0 - 4.0 GAIN (dB) - 6.0 - 8.0 - 10.0 - 12.0 - 14.0 - 16.0 - 18.0 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 FREQUENCY (kHz) GUARANTEED PERFORMANCE TYPICAL PERFORMANCE GUARANTEED PERFORMANCE
Figure 21. ML145502 Low-Pass Filter Response Receive
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ML145502, ML145503, ML145505
LANSDALE Semiconductor, Inc.
2.048 MHz 18 pF 10 M +5V 300 2.048 MHz (TDC, RDC, CCI) 18 pF
VCC 0.1 F GND Q8
R
OSC IN
OSC OUT 1
OSC OUT 2
MC74HC4060 Q4
8 kHz (TDE, RCE, MSI)
+5V VCC 1/2 MC74HC73 GND R
J
Q
J
1/2 MC74HC73 R +5V
Q
K
Q
K
Q
255 2.048 MHz
256
1
2
3
4
5
6
7
8
9
10
8 kHz
Figure 22. Simple Clock Circuit for Driving ML145502/03/05 Codec-Filters
Page 17 of 26
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ML145502, ML145503, ML145505
LANSDALE Semiconductor, Inc.
N=1
VAG R0 RxO
VDD RDD RCE RDC TDC TDD TDE VLS
R0 - 48 V N=1
N=2 10 k
+ Tx TxI 10 k - Tx Mu/A PDI VSS
MC145503
23a. Simplified Transformer Hybrid Using ML145503
N=1 R0 - 48 V N=1
VAG R3 RxO N=2 R4 R5 R6 R2 - Tx R1 TxI + Tx
VDD RDD RCE RDC TDC TDD TDE VLS
R0 = R3 R4 (R2 + R1) R3 R4 AV out = R0 R4 (R2 + R1) R3 + R0 R4 (R2 + R1) R0 R4 R3 + R0 R4
Mu/A PDI VSS
AV in = - R1 R2
MC145503
NOTE: Hybrid Balance by R5 and R6 to equate the RxO signal gain at Txl through the inverting and non-inverting signal paths.
23b. Universal Transformer Hybrid Using ML145503 Figure 23. Hybrid Interfaces to the ML145503 PCM Codec-Filter Mono-Circuit
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ML145502, ML145503, ML145505
LANSDALE Semiconductor, Inc.
R0 = 600
R0 = 900
+ Vref VSS N=1 R5 R0 N=2 R6 - 48 N=1 R0 R3 RxO + Tx TxI R2 R1 - Tx NOTE: Balance by R5 and R6 to equate the Txl gains through the inverting and non-inverting input signal paths, respectively, is given by: R1 R3 1- 2 x R2 R4 = 1+ R1 R2 R6 R3 - R5 + R6 R4 R5 R5 + R6 Mu/A PDI VSS RxO R4 RxG VAG
RSI VDD RDD RCE RDC TDC CCI TDD TDE MSI VLS
Tx Gain = R1/R2 Rx Gain = 1 + R3/R4 R5, R6 10 k Adjust Rx Gain with R3 Adjust Tx Gain with R1
ML145502
24a. Universal Transformer Hybrid Using ML145502
R0 = 600 T N=1 10 k R0 N=2 20 k RxG - 48 R N=1 R0 RxO + Tx TxI 20 k - Tx 10 k Mu/A PDI VSS TDD TDE MSI VLS CCI + Vref VSS VAG RxO RSI VDD RDD RCE RDC TDC
R0 = 900
ML145502
24b. Single-Ended Hybrid Using ML145502 Figure 24. Hybrid Interfaces to the ML145502 PCM Codec-Filter Mono-Circuit
Page 19 of 26
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Page 20 of 26
1N4002 1 VCC 2 0.0047 75 BP 15 TSI 5 CC 19.6 k 6 RS I BN EN HST VQB 10 VEE 1 k 0.1 10 F + 50 V - 48 V 11 R7 270 k -5V RS O 1 2 TSO 13 +5V 7 8 47 k 9 HSO 14 R3 42.2 k PDI 0.47 (A1) 10 k 10 k 5 6 7 8 0.1 TxO 4 19.6 k TIP125 3 16 R4 19.6 k R2 143 k EP RxI 17 (A0) 0.47 VAG R1 30.1 k 2 3 R5 126 k 4 TxI -Tx Mu/A PDI VSS RDC 13 TDC 12 TDD 11 TDE 10 V LS 9 18 1 MC3419-1L ML 145503 VAG RxO +Tx VDD 16 RDD 15 RCE 14 +5V 0. 1 75 TIP111 0.0047 1N4002
ML145502, ML145503, ML145505
- 48 V
TIP
Figure 25. A Complete Single Party Channel Unit Using MC3419 SLIC and ML145503 PCM Mono-Circuit
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RING
0.0047
LANSDALE Semiconductor, Inc.
Issue Aj
Page 21 of 26
+5V R23 D5 SPEAKER R24 MC34119 C13 C14 C12 9 5 VO1 8 V 6 O2 VCC 7 GND 4 V in 1 CD 3 FC1 2 FC 2 ML145406 R25 C15 1 10 11 13 12 14 15 8 VDD DI3 DO3 DO2 DI2 DI1 DO1 VSS +5V R37 - R41 SW3 - SW7 VCC T x3 Rx3 Rx2 Tx2 Tx1 Rx1 G ND 16 7 6 4 5 3 2 FEMALE DB-25 +5V 3 4 R3 5 X2 Q5 SW2 SW1 Q2 R15 R34 R14 Q1 MC145412 VDD 9 R36 C1 R11 R13 R12 LED 1 ML145428 +5V C8 C1 C2 C3 R1 R2 R3 R4 DTMF OUT TSO OSC C4 OSC MS MO VSS OH OPL 2 NC 8 10 11 6 12 17 -5V +5V 1 20 TxS VDD 17 4 DOE BRCLK 14 3 DL DIE 2 9 SB TxD 11 6 BR1 RxD 12 7 B R2 RxS 19 8 RST BR3 5 15 DCLK BCLK 18 16 CM DCO 13 10 VSS DCI C7 X1 R16 C6 TIP MC145426 ML145503 5 6 4 16 2 3 1 9 Tx- /A TxI VDD RxO Tx+ VAG V LS PDI TDC RDC RCE RDD TDD TDE VSS R10 -5V SYNC TO POWER SUPPLY C4 7 12 13 14 15 11 10 8 +5V C10 9 8 7 6 17 13 14 18 19 12 22 16 11 15 10 20 4 21 3 5 SO2 SI2 SO1 SI1 CLK TE1 Tx Rx RE 1 TE VSS VDD X2 PD X1 /A LO2 LB LO1 LI VD Vref 2 C9 TO POWER SUPPLY V in C11 RING
ML145502, ML145503, ML145505
SW1: CLOSED = ON-HOOK OPEN = OFF-HOOK
+5V
123 456 789 *0#
5 16 15 14 13 18 7
Figure 26. Digital Telephone Schematic
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R8
R7
R9
C3
C2
R6
R5
R3
R4
R2
R1
C5
HANDSET
Refer to AN968 for more information.
LANSDALE Semiconductor, Inc.
Issue A
ML145502, ML145503, ML145505
LANSDALE Semiconductor, Inc.
Table 3. Mu-Law Encode-Decode Characteristics
Normalized Encode Decision Levels 8159 1 7903 ... ... 8 16 256 4319 1 4063 ... 7 16 128 2143 1 2015 ... ... 6 16 64 1055 1 991 ... ... 5 16 32 511 1 479 ... 4 16 16 239 1 223 ... ... 3 16 8 103 1 95 ... ... 2 16 4 35 1 31 ... 1 15 2 3 1 1 1 1 0 NOTES: 1. Characteristics are symmetrical about analog zero with sign bit = 0 for negative analog values. 2. Digital code includes inversion of all magnitude bits. 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 2 ... ... 1 1 0 1 1 1 1 33 ... 1 0 1 1 1 1 1 99 ... 1 0 0 1 1 1 1 231 ... ... 0 1 1 1 1 1 1 495 ... 0 1 0 1 1 1 1 1023 ... 0 0 1 1 1 1 1 2079 ... ... 0 0 0 1 1 1 1 4191 ... 0 0 0 0 0 0 0 8031 Digital Code 1 Sign 2 Chord 3 Chord 4 Chord 5 Step 6 Step 7 Step 8 Step Normalized Decode Levels
Chord Number
Number of Steps
Step Size
Page 22 of 26
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ML145502, ML145503, ML145505
LANSDALE Semiconductor, Inc.
Table 4. A-Law Encode-Decode Characteristics
Normalized Encode Decision Levels 4096 1 3968 ... ... 7 16 128 2176 1 2048 ... ... 6 16 64 1088 1 1024 ... ... 5 16 32 544 1 512 ... ... 4 16 16 272 1 256 ... ... 3 16 8 136 1 128 ... 2 16 4 68 1 64 ... ... 1 32 2 2 1 0 NOTES: 1. Characteristics are symmetrical about analog zero with sign bit = 0 for negative analog values. 2. Digital code includes alternate bit inversion, as specified by CCITT. 1 0 1 0 1 0 1 1 ... 1 1 1 0 1 0 1 66 ... ... 1 1 0 0 1 0 1 132 ... 0 0 1 0 1 0 1 264 ... 0 0 0 0 1 0 1 528 ... 0 1 1 0 1 0 1 1056 ... 0 1 0 0 1 0 1 2112 ... 0 1 0 1 0 1 0 4032 Digital Code 1 Sign 2 Chord 3 Chord 4 Chord 5 Step 6 Step 7 Step 8 Step Normalized Decode Levels
Chord Number
Number of Steps
Step Size
Page 23 of 26
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ML145502, ML145503, ML145505
LANSDALE Semiconductor, Inc.
OUTLINE DIMENSIONS
P DIP 16 = EP (ML145503EP, ML145505EP) PLASTIC DIP CASE 648-08 -A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0 10 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0 10 0.51 1.01
B
1 8
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
P DIP 22 = WP (ML145502WP) PLASTIC DIP CASE 708-04
NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. MILLIMETERS MIN MAX 27.56 28.32 8.64 9.14 3.94 5.08 0.36 0.56 1.27 1.78 2.54 BSC 1.02 1.52 0.20 0.38 2.92 3.43 10.16 BSC 15 0 1.02 0.51 INCHES MIN MAX 1.085 1.115 0.340 0.360 0.155 0.200 0.014 0.022 0.050 0.070 0.100 BSC 0.040 0.060 0.008 0.015 0.115 0.135 0.400 BSC 15 0 0.020 0.040
22
12
B
1 11
A N
L
C K
H
G
F
D
SEATING PLANE
M
J
DIM A B C D F G H J K L M N
Page 24 of 26
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Issue A
ML145502, ML145503, ML145505
LANSDALE Semiconductor, Inc.
OUTLINE DIMENSIONS
PLCC 28 = -4P (ML145502-4P) PLCC PACKAGE CASE 776-02
B -N- Y BRK
0.007 (0.180) U
M
T L-M
M
S
N
S S
0.007 (0.180)
T L-M
N
S
D Z -L- -M-
W
28 1
D
X VIEW D-D
G1
0.010 (0.250)
S
T L-M
S
N
S
V
A Z R C
0.007 (0.180) 0.007 (0.180)
M M
T L-M T L-M
S S
N N
S S
H
0.007 (0.180)
M
T L-M
S
N
S
E G G1 0.010 (0.250)
S
K1 0.004 (0.100)
J
-T- VIEW S
SEATING PLANE
K F VIEW S 0.007 (0.180)
M
T L-M
S
N
S
T L-M
S
N
S
NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
DIM A B C E F G H J K R U V W X Y Z G1 K1
INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --- 0.025 --- 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 --- 0.020 2 10 0.410 0.430 0.040 ---
MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 --- 0.64 --- 11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 --- 0.50 2 10 10.42 10.92 1.02 ---
Page 25 of 26
www.lansdale.com
Issue A
ML145502, ML145503, ML145505
LANSDALE Semiconductor, Inc.
OUTLINE DIMENSIONS
SO 16 = -5P (ML145503-5P, ML145505-5P) SOG PACKAGE CASE 751G-02 -A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 10.15 10.45 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0 7 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.400 0.411 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0 7 0.395 0.415 0.010 0.029
-B-
1 8
8X
P 0.010 (0.25)
M
B
M
16X
D
M
J TA
S
0.010 (0.25)
B
S
F R X 45 C -T-
14X
G
K
SEATING PLANE
M
Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. "Typical" parameters which may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by the customer's technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
Page 26 of 26
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Issue A

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